This invention relates to an analog-to-digital comprising:
a first analog-to-digital converter for converting a first analog signal to a first digital signal which denotes the sub-range of a plurality of sub-ranges in which the first analog signal is situated,
a digital-to-analog converter converting the first digital signal to a second analog signal,
a second analog-to-digital converter for convening a difference signal indicative of the difference between the first and second analog signals to a second digital signal,
detection means for detecting an overflow and an underflow if the difference signal is situated above and below respectively, the sub-range denoted by the first digital signal, and
correction means for correcting the first digital signal in response to the detection of the overflow and underflow.
An analog-to-digital converter (ADC) of this type is known from U.S. Pat. No. 3,967,269 and is of a type known as a multistep or sub-ranging ADC. In this type of ADC the conversion to the desired digital output signal is performed in two or more steps while in each step a separate ADC converts an ever smaller subrange of the overall range of the analog input signal to be convened. In the prior art ADC, a coarse conversion of the first analog signal to be convened to the first digital signal is effected in the first ADC having an M-bit resolution. The first digital signal is reconverted to a second analog signal in the digital-to-analog converter. The difference between the second and first analog signals is then fine-convened to the second digital signal by means of the second ADC having an (N-M)-bit resolution. The M bits of the first and the (N-M) bits of the second digital signal are combined to provide the desired N-bit digital output signal, the bits of the first digital signal forming the most significant bits and the bits of the second digital signal forming the least significant bits of the output signal.
As a result of errors in the system the difference signal may come to be outside the analog sub-range determined by the first ADC. Such errors may be caused by, for example, decision errors in the first ADC. The prior art ADC comprises detection means signalling by means of an overflow signal or an underflow signal whether the difference signal has come to be above or below the sub-range as a result of an error. In the prior art ADC the error is corrected in the following manner. In the case of an overflow the second ADC produces a second digital signal which has a value reduced by a number equal to the maximum number of sub-ranges the second ADC is capable of measuring (fold-back) and in a digital arithmetic unit one bit is subtracted from the first digital signal. In the case of an underflow the second ADC produces a second digital signal which has a value increased by afore-mentioned number and in the digital arithmetic unit one bit is added to the first digital signal. If neither an underflow nor an overflow is detected, the difference signal lies within the range denoted by the first digital signal. In that case the second digital signal is produced by the second ADC unaltered, and no arithmetic operation is performed on the first digital signal by the digital arithmetic unit.
A disadvantage of this prior art error correction method is that the digital arithmetic unit has to be capable of both adding one bit to the first digital signal and subtracting one bit therefrom. The realisation of an arithmetic unit which is capable of performing both of these operations is complicated.